The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a highly integrated semiconductor memory device having a capacitor of large capacitance by using as an etching mask silicon oxide island formed via the pin hole of an insulating layer.
Increase in cell capacitance improves the read-out capability and decreases the soft error rate in a DRAM memory cell, and therefore plays an important role in the improvement of cell memory characteristics. Due to the increase in packing density of memory cells, unit cell area per chip has decreased, which in turn reduces the area available for the cell capacitor. Therefore, the capacitance per unit area must be increased in tandem with increase in packing density.
Recently, many research reports have been published concerning increase in cell capacitance, most of them relating to the structure of the cell capacitor's storage electrode. For example, they include: the fin-structured electrode (3-Dimensional Stacked Capacitor Cell for 16M and 64M DRAMS by T. Ema et al., IEDM 1988, pp.592-595) of Fujitsu Co., the Box structured electrode (A New Stacked Capacitor Cell with Thin Box Structured Storage Node by S. lnoue et al., Extended Abstracts of the 21st Conference on Solid State Devices and Materials, 1989, pp.141-144) and SSC (Spread-Stacked Capacitor) Cell (A Spread-Stacked Capacitor (SSC) Cell for 64 Mbit DRAMs by S. Inoue et al., IEDM 1989, pp.31-34) of Toshiba Co., and the cylindrical electrode (Novel-Stacked Capacitor Cell for 64 Mb DRAMs by W. Wakamiya et al., VLSI Techology Symposium, 1989, pp.69-70) of Mitsubishi Co. However, attempts to increase cell capacitance by improving the structure of the storage electrode, have met with problems such as design rule limitations and a high error rate due to complicated processes. Accordingly such improved structure storage electrode is not practical in use. Therefore, in order to overcome the aforesaid problems, the need for a new manufacturing method for a cell capacitor increases further.
A method for increasing cell capacitance has been proposed which utilizes the physical properties of the storage electrode independent of the structural improvement of the storage electrode.
For example, the technique to enlarge the surface of a storage electrode by providing a polycrystalline silicon layer having an uneven surface is disclosed on pages 869 to 872 by Yoshio Hayashide, et al. and pages 873 to 876 by H. Watanabe et al., both of which were published in a literature entitled "Extended Abstracts of the 22nd on Solid State Device and Materials" in 1990.
According to the method of Watandbe et al., polycrystal silicon is deposited at 550.degree. C. by a low-pressure CVD (Chemical Vapor Deposition) method. This specific temperature 550.degree. C. corresponds to a transition temperature in which a film structure changes from an amorphous to a polycrystal structure.
The surface area of a polycrystalline silicon layer deposited at the above temperature is twice that deposited at other temperatures. The capacitor of a semiconductor device is formed by using the above-deposited polycrystalline silicon.
According to the above method, the capacitance is doubled by applying the above polycrystalline silicon layer to the storage electrode of a stack-type capacitor. Also, Hayaside et al. teaches that capacitance is increased to one and an half times when compared with a conventional polycrystalline silicon electrode, when forming a storage electrode by depositing polycrystalline silicon at 575.degree. C.
Also, a capacitor cell having a storage electrode of in COB (Capacitor-Over-Bit line) structure with the above uneven surface is disclosed on pages 665 to 658 of IEDM (1990) in a paper entitled "A Capacitor Over-Bit Line (COB) Cell With a Hemispherical-Grain Storage Node for 64 Mb DRAMs" by M. Sakao, et al.
FIG. 1 is a layout used for manufacturing the COB cell described in the above paper.
The region designated by a laterally extending single-dotted line is a mask pattern P1 for forming an active region. The regions defined by solid lines and arranged symmetrically are a mask pattern P2 for forming gate electrodes. The doglegged region designated by long-dashed lines balancing around the center are a mask pattern P3 for forming local interconnections by which a source region is connected to a storage electrode. The region defined by a laterally extending double-dotted line which has a contact hole mark at its center, represents a mask pattern P4 for forming a bit line. The regions designated by short-dashed lines and filled with oblique lines are a mask pattern P5 for forming the storage electrode.
The COB cell is one where a cell capacitor is formed over a bit line, and its manufacturing process is as follows. After the bit line is formed to be connected to a drain region of a transistor, the bit line is electrically insulated by coating an insulating material on the whole surface of the substrate. Then, the insulating material is partially removed, thereby exposing a portion of the source region of a transistor. A storage electrode is formed on the insulating material, and is connected to the source region of the transistor through the exposed portion of the source region. This is suitable for 64 Mb and 256 Mb DRAM cells, and was introduced for preventing bit line contact failures.
FIGS. 2A to FIG. 2D are cross sectional views illustrating a method for manufacturing a highly integrated semiconductor device according to the conventional method, which correspond to a sectional view taken along line A--A' in FIG. 1.
The polycrystalline silicon with hemispherical-grain described in the above-mentioned paper (hereafter, referred to as "HSG polycrystalline silicon") is formed by means of physical phenomena, especially those occurring while amorphous silicon is transformed into polycrystalline silicon. When amorphous silicon is deposited on a semiconductor substrate and then heated, the amorphous silicon forms minute hemispherical-grains, under specific conditions: 550.degree. C. at 1.0 torr. The amorphous silicon becomes polycrystalline silicon in an intermediate state having an uneven surface, which increases the surface area to two or three times that of a smooth surface.
An insulating layer 22 (strictly speaking, two or three interposed insulating layers) is formed over the whole surface of the semiconductor substrate, on which both a local interconnection 20 in contact with the source region of a transistor and a bit line in contact with the drain region, have been formed. Thereafter, a contact hole 9 is formed by anisotropic etching in order to expose a portion of the local interconnection. Then, the contact hole is completely filled with polycrystalline silicon which is formed to a predetermined thickness on the insulating layer. Finally, an etching process is performed, using the above mask pattern P5, whereby a core storage electrode 30 is formed per each cell unit (FIG. 2A).
An HSG polycrystalline silicon layer 32 is formed over the whole surface of the semiconductor substrate on which the core storage electrode 30 has been formed. This is formed by an ordinary CVD method (Low-Pressure Chemical Vapor Deposition), under specific conditions of temperature and pressure, i.e., at 550.degree. C. and 1.0 torr. Because of the small hemispherical grains, the surface area of the HSG polycrystalline silicon layer is increased to roughly twice that of conventional polycrystalline silicon layers without the HSG. Here, since the HSG is about 80 nm in diameter, the HSG polycrystalline silicon layer should be at least 80 nm thick and narrower than half of the core storage electrode spacing (FIG. 2B).
The HSG polycrystalline silicon layer 32 is etched back by an RIE (Reactive Ion Etching) method, using HBr gas without any etching masks. This is carried out until portions of the surface of insulating layer 22 between each core storage electrode 30 are exposed to define the storage electrode by cell units. At this step, the HSG polycrystalline silicon layer coated on the upper surface of the core storage electrode is completely removed and its uneven surface is transmitted to the surface of the core storage electrode. The HSG polycrystalline silicon 32a coated on the side surfaces of the core storage electrode is somewhat smoothed. The storage electrode is constituted by the core storage electrode 30a having the uneven surface and the HSG polycrystalline silicon layer 32a remaining after the etching process (FIG. 2C).
After a dielectric film 34 is formed on the whole surface of the storage electrode, a plate electrode 36 is formed by coating polycrystalline silicon on the whole surface of the semiconductor substrate, whereby the cell capacitor is completed (FIG. 2D).
In the above-described method for manufacturing a capacitor of a memory cell, the physical properties of the material are used, independent of the structural improvement of the storage electrode, to extend the effective area of the cell capacitor. Therefore, a cell capacitor is manufactured by a simplified process free from design rule. However, the required process conditions, such as the specific temperature and pressure, demand that the margin of error during processing becomes overly narrow. Moreover, its increase of effective capacitance per unit area is limited to approximately two times that of previous methods.